Sr. Engineer, Digital Design – SiTime

Sr. Engineer, Digital Design job in Netherlands

Company
SiTime is a leading precision timing company specializing in MEMS-based semiconductor solutions. Their innovative timing technology offers superior performance, size, power efficiency, and reliability, enabling customers to differentiate their products in various industries, including automotive, networking, and consumer electronics.

Position
The Sr. Engineer, Digital Design will develop advanced digital circuits for MEMS-based timing solutions. The role involves micro-architecture design, RTL development, synthesis, and post-silicon validation, ensuring high performance and low-power operation.

Key Responsibilities
• Develop micro-architecture specifications for digital circuits based on product requirements.
• Design Register Transfer Level (RTL) logic using Verilog/SystemVerilog.
• Create standalone test benches and verify RTL behavior.
• Write and validate SystemVerilog Assertions (SVA).
• Define timing constraints and clock definitions for synthesis and place-and-route.
• Run synthesis tools and troubleshoot timing issues.
• Analyze timing/area/power trade-offs and optimize designs.
• Conduct Static Timing Analysis (STA) and debug issues.
• Collaborate with cross-functional teams (analog, verification, backend, system, and test engineers).
• Support post-silicon bring-up, validation, and debugging.

Requirements
• Master’s degree in Electrical Engineering with 5+ years of relevant industry experience.
• Proficiency in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals (e.g., clock dividers, multi-clock designs, CDC, FIFO, FSM).
• Experience in mixed-signal digital design.
• Understanding of discrete-time signal processing, FIR, and IIR filter design.
• Strong grasp of digital design flow, including RTL design, synthesis, and Static Timing Analysis (STA).
• Scripting skills in Perl, Tcl, or Python.
• Excellent verbal and written communication skills in English.
• Ph.D. in Electrical/Computer Engineering (preferred) with 3+ years of industry experience.
• Experience in high-precision digital arithmetic logic and DSP (2-5 years).
• Background in Digital Phase-Locked Loops (DPLL) design.
• Knowledge of low-power digital design and control theory.
• Familiarity with MATLAB, Simulink, or similar modeling tools.

Browse more SemiconductorJobs in Europe here